SLE believes that our people are our greatest asset. We value contributors with strong technical ability who thrive in a stimulating, team-centric corporate culture.
While Silicon Logic Engineering, Inc. appreciates the interest of all candidates, only those meeting the specific position requirements may be contacted. Principals only; no recruiters please.
Click here for current positions open at SLE.
Examples of positions SLE has hired for in the past include:
IC Technologist
Design responsibilities include developing design ground rules based on the IC technology, CAD methodology, design architecture, and design performance requirements. Additional responsibilities include synthesis and static timing analysis close cooperation and coordination with the physical design team on ASIC implementation details, and interfacing with customers and technology vendors. The qualified candidate will be knowledgeable in modern CMOS technologies, will have experience with ASIC technologies at 0.13um or smaller nodes, will have experience with synthesis and static timing tools and methodologies, and will have a working knowledge of HSPICE. Additional experience with high-speed design (500MHz), high gate-count design (10M gates), and high-speed signal integrity analysis is a plus.
ASIC Logic Design Engineer
Design responsibilities include architectural and RTL design of complex, multi-million gate ASICs; logical and physical synthesis; logic simulation; and an understanding of static timing analysis and floorplanning techniques. The qualified candidate will be knowledgeable in Verilog and/or VHDL, industry-standard simulators (VCS, MTI, NC-Verilog), and in design flows starting from a high-level specification through gate-level netlist. Additional experience with System Verilog, C/C++ and Java is a plus.
ASIC Verification Engineer
Responsibilities include development of test environments and tests to enable functional verification of large, multi-million gate ASICs. Additional responsibilities include verification plan development, code coverage analysis, formal equivalency checking, and behavioral modeling. The qualified candidate will be knowledgeable in Verilog and/or VHDL; C/C++, Java, or other programming languages; industry-standard simulators (VCS, MTI, NC-Verilog); gate-level simulation techniques; and logic debug. Additional experience with formal verification tools, hardware design and debug, constrained-random verification techniques, and System Verilog is a plus.
ASIC Signal Integrity Engineer
Responsibilities include HSPICE analysis of system-level interconnect paths for high-speed (multi-GHz) signaling between advanced ASICs, with an emphasis on maintaining acceptable signal integrity and noise margin. Additional responsibilities include working with designers on the on-chip driver and receiver design specifications and implementation to enable this high-speed communication. The qualified candidate will be knowledgeable in high-speed interconnect concepts, including crosstalk analysis, attenuation, dispersion, SSO, and ISI, and will have experience with HSPICE. Additional knowledge regarding advanced ASIC design, on-chip signal integrity issues, high-speed clock design, and 3D extraction is a plus.
ASIC Physical Design Engineer
Design responsibilities include floorplanning, gate placement, clock tree design and implementation, power grid design and implementation, routing, physical verification (LVS/DRC), on-chip signal integrity analysis (EM, IR drop, xtalk, antennas, etc.), and GDSII generation. Additional responsibilities include working closely with logic designers to enable physical synthesis based on the floorplan. The qualified candidate will be knowledgeable in industry-standard place & route flows (Synopsys Astro/Synopsys ICC). Experience with high-speed (500MHz), large (>10M gates) ASIC designs is a plus.
ASIC DFT Engineer
Responsibilities include test insertion on large, multi-million gate ASICs (including mux-scan FF, LSSD, 1149.1 boundary scan, memory BIST, and logic BIST), test logic functional verification, and test vector generation (ATPG, IDDQ, transition fault, parametric, etc.). The qualified candidate will be knowledgeable in industry-standard test tools (Synopsys DFT Compiler, BSD Compiler, TetraMax preferred), Verilog and/or VHDL, industry-standard simulators (VCS, MTI, NC-Verilog), and gate-level netlist manipulations.
Senior ASIC Verification Engineer
Responsibilities include leading the verification team for complex ASIC projects. The team and leader will develop test environments and tests to enable functional verification of large, multi-million gate ASICs. Additional responsibilities include verification plan development, code coverage analysis, formal equivalency checking, and behavioral modeling. The qualified candidate will have at least 7 years experience verifying ASICs and will be knowledgeable in Verilog and/or VHDL; C/C++, Java, or other programming languages; industry-standard simulators (VCS, MTI, NC-Verilog); gate-level simulation techniques; and logic debug. Additional experience with formal verification tools, hardware design and debug, constrained-random verification techniques, and System Verilog is a plus.
