SLE’s Interlaken protocol is a scalable, high-speed chip-to-chip interface protocol that combines the advantages of the popular SPI4.2 and XAUI interfaces. It builds on the channelization and per channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high speed SERDES technology, similar to XAUI.
SLE’s scalable Interlaken IP Core provides from 10Gbps to over
150Gbps of bandwidth. This scalability ideally suits Interlaken for
multiple generations of future network switches, routers and storage
equipment. The scalability is achieved through the combination of
SerDes speed (3.125Gbps to 6.375Gbps) and a variable number of
SerDes lanes (1 to 24).
Design and tested to be easily synthesizable into many ASIC
technologies, SLE’s Interlaken IP Core was uniquely built to
work with off-the-shelf SerDes from most leading technology
vendors. Using the vendor specific proven SerDes allows SLE
Customers to quickly integrate the Interlaken IP Core into the
customer’s technology of choice.
Interlaken Top Level Block Diagram:
Highlighted Features
- Conforms to Interlaken Protocol Definition, rev. 1.1
- Support for 256 communications channels, plus 8 bit channel extension for up to 64K channels
- SerDes lanes may be individually enabled/disabled
- Supports the full range of Interlaken SerDes speeds (3.125Gbps to 6.375Gbps)
- A simple control word structure to delineate packets, similar in function to the SPI4.2
- A continuous Meta Frame of programmable frequency to guarantee lane alignment, synchronize the scrambler, perform clock compensation, and indicate lane health.
- Protocol independence from the number of SerDes lanes and SerDes rates.
- 64B/67B data encoding and scrambling.
- Performance that scales with the number of lanes 1 to 24
- Ability to disable SerDes lanes
- Three options for User Interface (128 bit, 256 bit, and 2x256 bit) allows for high bandwidth operation with relatively low user clock speed.
- CRC24 and CRC32 generation and checking for burst and lane integrity
- BUSTMAX size can be configured from 64 bytes up to 512 bytes
- BUSTMIN size can be configured from 32 bytes up to 256 bytes
- Support for both in-band and out-of-band flow control
- TX to RX loopback paths on both the data and flow control
- RX to TX loopback paths on both the data and flow control
- Error detection on user interface to detect illegal burst sizes and other errors
- Configurable error injection mechanisms for testability
- Both packet mode and segment mode support
- Generic SerDes interface can attach to SerDes for many different vendors, paramerterizable width can support 8, 10, 16, or 20 bit
- Built-in interrupt structures
- Maintenance interface for control and configuration, interrupts and status, SerDes debug, programmable calendar and flow control, and Statics counters
More Information
The open Interlaken specification was co-written by Cortina
Systems and Cisco Systems to provide a far more scalable chip-to-chip
interface protocol than previous protocols. Interlaken combines the
advantages of the popular SPI4.2 and XAUI interfaces by building on
the channelization and per channel flow control features of SPI4.2,
and reducing the number of chip I/O pins by using high speed SERDES
technology, similar to XAUI.
For more information regarding the Interlaken Technology see the
Interlaken Whitepaper: Interlaken
Technology: New Generation Packet Interconnect Protocol
The SLE licensable Interlaken IP is available through SLE's sales network. For sales related questions, contact sales at sales@siliconlogic.com or call SLE at 1-908-580-1870.
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