SLE's Think Physical™ design process allows SLE's team to accurately predict the effects that back-end process have on physical design closure. Combining the team’s experience, knowledge, and databases, the engineers plan for these effects from the beginning, and implement the design to prevent or minimize the effects' impact on physical design closure. The process continues to evolve with today's latest technologies and EDA design tools and has delivered over 35 right-first-time complex ASIC designs.
SLE's Think Physical design process is more than a methodology - it's a philosophy. To some, the process is counter-intuitive, since too often the first thing a team of engineers plan to do is write RTL.
The process is slightly different for FPGA design versus ASIC design, but the philosophy and some of the techniques remain the same.
Think Physical ASIC process advocates that design teams start by outlining the entire design flow, from architecture all the way through to tape-out, before any code is written. This allows all the team members to understand how the specific constraints of the architecture, the technology, the verification environment, the synthesis flow, and the place & route flow mutually interact and affect the tasks associated with each group on the team. As a result of the early planning, the overall system and design process is streamlined and design closure is easier to achieve.
SLE's Think Physical design process has its roots in the supercomputer industry, where high performance, large gate count ASICs have been the norm for years. The concepts inherent within the process have evolved as technology has improved. Today, SLE's engineers take advantage of the latest EDA tools and focus their energy on finding solutions to the new problems associated with today's deep-submicron CMOS technologies.
While the process is evolutionary, the results are revolutionary - designs that work!
If you have questions about SLE's Think Physical design process, please contact us.
