SLE's DelayBlaster™ is a timing optimization tool used in the ASIC design cycle to optimize critical paths, meet timing specifications, and produce zero negative slack. DelayBlaster works in conjunction with industry standard static timing and physical design tools to significantly reduce the amount of time it takes to converge on timing closure.
Highlighted Features:
- Integration with industry-standard tools via simple text-based files
- Simple yet effective algorithms mean fast run-times with excellent QoR
- Exact correlation with the static timing tool, since DelayBlaster uses timing data from the static timing tool directly
- Flexible input parameter file allows user to easily control which violations are looked at, as well as the types of fixes that can be implemented
- Proven for use with large, complex ASICs (10M+ gates, 400+ MHz)
- Preservation of logic with a “dont_touch” attribute
- Ability to process hierarchical or flat designs
- Correction of technology violations, either implicitly or explicitly, during an optimization run
More Information:
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