Two operations are supported by the Floating Compare Unit:
- IEEE Compliant Floating Compare
- Non-IEEE Compliant Floating Compare
The first of these operations follows the IEEE 754 Standard for Floating Point Arithmetic for Single Precision (32-bit) Comparison. The second does so with the exception that Denormals are treated as like-signed Zeros. An additional exception flag is provided to signal when a Denormal input is present.
Compare results are encoded on two outputs: Greater, and Less. When both are active, the Unordered case is signaled. When neither is active, the Equal case is signaled.
NaN formats may be specified with a configurable QNaN bit value and bit position, and a default QNaN may be specified for Invalid results.
The Floating Compare Unit is a fully combinational unit. Its latency is so short that it should never require the addition of pipeline registers.
Highlighted Features
- IEEE Single Precision Floating Point Compare
- IEEE-like Single Precision Floating Point Compare (Denormals treated as Zeros)
- Fully Combinational Design
Applications
- Microcontrollers
- Microprocessors
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