he Floating Point Divide Unit is optimized to exclusively support the division operation. The divider core uses an SRT algorithm to provide two quotient bits per clock cycle. A ‘go’ signal causes the unit to reset, capture the input operands, and to begin the division process. A ‘done’ signal is provided to signal that the result is ready. The ‘done’ signal can be configured to appear immediately when a Zero, QNaN, or Infinity result can be determined directly from the input operands.
The operation of this unit follows the IEEE 754 Standard for Floating Point Arithmetic for Single Precision (32-bit) arithmetic for division with the exception that Denormals are treated as like-signed Zeros. An additional exception flag is provided to signal when a Denormal input or what would have been a Denormal output is flushed to Zero. Results for exceptions are the IEEE Standard default results as defined for when no trap occurs.
NaN formats may be specified with a configurable QNaN bit value and bit position, and a default QNaN may be specified for Invalid results.
The signaling of Underflow is configurable for the detection of tininess either before or after rounding.
Highlighted Features
- IEEE-like Arithmetic (Denormal treated as Zeros)
- IEEE Single Precision Format
- Fully Synchronous Design
- All outputs registered
- Minimal combinational logic on inputs
- 15-clock pipeline rate
- 17-clock latency
Applications
- Microcontrollers
- Microprocessors
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