The development of new FPGA technology and designs, like complex ASIC designs, requires experienced engineers to take critical design considerations into account.
SLE specializes in large gate count designs, high clock rate designs, FPGA to ASIC efficient portability, and FPGA system architecture considerations.
SLE’s team of experienced engineers utilizes our Think Physical™ process to create the highest-quality FPGA designs by using leading-edge verification techniques and by planning for the effects that the back-end process can have on design closure. By using an ASIC based process, the team implements the design to create a high-quality, efficient design that works.
Creating high-quality, efficient designs means creating designs that meet speed and power requirements within the FPGA within the product schedule. When ported to an ASIC, these high-quality, efficient designs are better optimized resulting in an efficient, higher-yield ASIC.
Significant cost savings and schedule savings are realized for customers that require:
- A high volume, high density design that tests the limits of current FPGA technology,
- A high-quality prototype or beta hardware,
- An efficient design that may be ported to ASIC (efficiency increases yield) as the market justifies it.
FPGA Product Definition
FPGA Design
- RTL code generation (VHDL, Verilog)
- High-speed interface design
- Multiple clock domain design
- Logic synthesis
- Vendor fuctional macros
- IP block integration
FPGA Verification
- Testbench generation
- Functional simulation
- Post-Synthesis simulation
- Constrained random verification
- Assertions
FPGA Compilation and Analysis
- Partitioning
- Clock optimization
- Design translation
- Synthesis optimization
- I/O planning and analysis
- Static timing analysis
- Design closure
FPGA Design Delivery
- RTL design source files
- Simulation test bench
- Suite of verification tests
- Implementation specification
- Verification plan and checklist
- CAD tools, scripts, and log files
