SLE's ScanBlaster™ utility enables optimal scan insertion on very large, complex designs without compromising performance. ScanBlaster is compatible with industry standard test insertion tools that provide basic functions (e.g. replacement of non-scan elements with scan elements). In addition to connecting pre-existing scan segments, ScanBlaster significantly reduces congestion and improves timing closure by considering ASIC floorplans when connecting scan elements. This early consideration of physical effects means that ScanBlaster is particularly well suited to large, high-speed designs with unique testability requirements.
Highlighted Features
- Design partitioning into ‘chiplets’ (small physically local regions) to give better performance, less congestion, and better timing
- SCAN_IN and SCAN_OUT pins are used as anchors to help determine ordering of scan chains to avoid unnecessarily long scan routes
- Register placement information can be used to control scan insertion down to the register level if desired
- Scan tracing function is useful for planning scan architecture
- On-chip memory structures are dealt with separately to allow user to control how their scan chains are connected with other scan elements
- Scan connections to pre-wired chains or to custom cores and blackboxes supported via attributes on the designs
- Registers within different clock domains can be easily isolated to minimize the number of resynchronization flops required
- Test logic and functional logic can be isolated (e.g., boundary scan or BIST logic)
- Muxed-scan flip-flop and LSSD design styles supported
- Scan chain order within full or partial chains can be preserved
- Tcl interface for several industry-standard tools
More Information
Contact Lonnie Heidtke for more information.
