- ASIC Design: SLE is the most experienced leading-edge ASIC design center team.
- System Design: SLE's team offers system design expertise to complement leading-edge ASIC design.
- ASIC Metholology: SLE's experienced ASIC design experts have developed and are continuously improving an ASIC design methodology that works- Think Physical™. All designs have been right-first-time. Leading-edge design work includes, for example, 60+ million gate custom ASICs, 60nm, with custom and standard blocks.
- ASIC Toolsuite: As part of SLE's proven and repeatable ASIC design methodology, SLE has developed a complementary toolsuite that works with standard tools to sucessfully complete the largest, most complex ASIC designs.
- ScanBlaster: This ASIC tool works with industry tools to enables optimal scan insertion on very large, complex designs without compromising performance.
- DelayBlaster: This ASIC tool is a timing optimization tool used in the ASIC design cycle to optimize critical paths, meet timing specifications, and produce zero negative slack.
- StackBlaster: This ASIC tool is a placement optimization tool that gives users the ability to very finely control cell placement on large, complex ASIC designs.
SLE's Product Development Consulting Services provide high-level ASIC, FPGA, and electronic system development guidance to companies that are developing very complex designs, government organizations, and investment companies.These services help decision makers manage the risks associate with high-end design.
Semiconductor Intellectual Property Cores
- Interlaken:SLE’s Interlaken protocol is a scalable, high-speed chip-to-chip interface protocol that combines the advantages of the popular SPI4.2 and XAUI interfaces.
- SPI-4 Phase 2:The SPI-4 Phase 2 (System Packet Interface Level 4 Phase 2) is a high-speed interconnection for 10 Gb/s aggregate bandwidth applications.
- Serial RapidIO Endpoint:The RapidIO Endpoint IP is compliant with the RapidIO Interconnect Specification (Revision 1.3)and has proven interoperability.
- PCI 2.2:The PCI Core is a highly configurable interface block to allow efficient communication between a PCI 2.2 Local Bus and User Application logic.
- Floating Point Units:All of SLE's Floating point units feature IEEE-like Arithmetic (Denormals treated as Zeros) and IEEE single precision format.
SLE specializes in high-end, right-first-time ASIC design services.
- Unique Focus:SLE is uniquely focused on high-end design services.
- Executive Team:SLE is led by a team of semiconductor industry veterans.
- Testimonials:Customer Survey revealed overwhelmingly positive responses.
- FAQs:Frequently asked questions about SLE and our ASIC design expertise.
- Careers: SLE's ASIC and FPGA Career Opportunities.
- News: News about SLE's ASIC and FPGA Services, Products, and Business.
- Papers: Papers authored by SLE engineers.
- Contact Us: Here is our contact information.
- Directions: Need a map or directions? Here they are.
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