How can a systems-developer know how a purchased SPI-4.2 IP core will perform in a complex, high-speed networking system?
SLE is reducing the chance of IP failure by providing a FREE encrypted Verilog SPI-4.2 functional model packaged within a demonstration simulation for SPI-4 Phase 2 implementation.
The built-in traffic generator exercises the model under typical data patterns and controls are provided to exercise the deskew logic. The SLE SPI-4.2 Model Simulation provides visibility into the SLE-developed core with cycle-accurate models that can be exercised, observed, and evaluated for potential integration into a target application.
The SLE SPI-4 Phase 2 Model Simulation has helped designers improve their overall understanding of SPI-4.2 functionality and has demonstrated how well the SLE-developed core works in complex, high-speed networking systems.
About SLE's SPI-4 Phase 2:
SLE's SPI-4 Phase 2 core is fully compliant with the Optical Internetworking Forum's (OIF) SPI-4 Phase 2 standard, also known as POS-PHY(tm) Level 4 (PL4) interface. Used to accelerate data movement and reduce bottlenecks, the SPI-4 Phase 2 interface provides an ideal solution for packet and cell transfer in applications such as OC-192, Packet over Sonet/SDH, and 10 Gigabit Ethernet.
Also, because interoperability is a fundamental requirement of today's high-speed interfaces, the SLE-developed SPI-4.2 core has been proven interoperable with the similar offerings from leading ASSP developers and is available in 13 different technologies.
SLE includes the encrypted Verilog for the SPI-4 packet generator and the SPI-4 protocol checker. The Packet Generator, when added to a Verilog test bench, generates valid SPI-4 data packets to be transmitted over the channel. The Protocol checker verifies that the data being sent across the channel meets the OIF protocol standard.
Using SLE's SPI-4 Phase 2 IP product offerings, designers can significantly reduce implementation costs and accelerate their time-to-market compared to in-house or full-custom design alternatives.
Download the brief datasheet, about SLE's SPI-4 Phase 2. A technical article written by Mike Berry, and published by EDN details what architectural and design requirements are needed for an OIF compliant SPI-4 Phase 2 core to address the speed and interoperability requirements of today's systems. You can also read about the proper configuration and usage of the SPI-4 in a paper written by Kelly Marquardt and published by CommsDesign.com.
The SLE SPI-4 Phase 2 core is available immediately. SLE also offers a complete suite of design services to speed the integration of SIP into your system. Contact Lonnie Heidtke for more information.
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Accessing SLE's SPI-4.2 cores:
Evaluate SLE's SPI-4 Phase 2 cores for FREE by emailing SLE. The SLE SPI-4 Phase 2 Model Simulation works on Solaris and Linux operating system environments and you can choose between one of three different Verilog simulator environments: Synopsys VCS, Cadence Verilog-XL, or Model Technology ModelSim.
Click here to email SLE for SPI-4.2 Model Simulation
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