Serial RapidIO Endpoint IPTM
The RapidIO® Interconnect Architecture is an industry-standard, high performance, packet-based interconnect technology that provides a high-speed interconnect between network processing units (NPUs), central processing units (CPUs), and digital signal processors (DSPs). It addresses the need for a standards-based, high-speed, reliable interconnect and is targeted at the networking, embedded, and storage markets. RapidIO allows chip-to-chip, board-to-board, and system-to-system communications scaling to 10 Gbps and beyond.
Tundra Semiconductor is the industry's leading supplier of RapidIO® System Interconnect Solutions, providing a broad portfolio of switches and development platforms for the growing RapidIO market. SLE, Tundra's Design Services Division, will be offering and supporting the Tundra Serial RapidIO Endpoint Intellectual Property (IP). Leveraging Tundra's Serial RapidIO IP library will enable customers to enjoy the benefits of RapidIO - a high performance, packet-oriented interconnect protocol for chip-to-chip, board-to-board, and chassis-to-chassis applications - in their designs. With the RapidIO Endpoint IP and SLE's design services, customers can access a full service RapidIO solution to create a customized application while lowering design risk and accelerating time-to-market.
The RapidIO Endpoint IP is
compliant with the RapidIO Interconnect Specification
(Revision 1.3). It has proven interoperability between
various endpoints in customers' designs to be fully
interoperable with Tundra's Serial RapidIO portfolio,
including the Tsi578TM, Tsi576TM, Tsi574TM, Tsi568ATM, and Tsi564ATM switches. This RapidIO Endpoint IP also works with off-the-shelf SerDes IP from leading technology vendors. The ability to use proven SerDes IP, coupled with proven Serial RapidIO Endpoint IP, means fast RapidIO integration into your design. Ease of IP integration reduces development cost and time resulting in your end product reaching the target market faster. The Tundra RapidIO Endpoint IP is specifically designed and tested to be easily synthesizable into 130 nm (or better) CMOS technology.
SRIO Top Level Block Diagram:
Highlighted Features
- Compliant with RapidIO Interconnect Specification (Revision 1.3)
- Configurable modes of operation:
- 4x/1x mode and 1x mode
- 3.125 Gbaud/s, 2.5 Gbaud/s, 1.25 Gbaud/s
- Physical Coding Sub-layer (PCS)
- 8B/10B encode/decode
- Physical Medium Attachment (PMA)
- 66, 50, or 34-bit addressing on the RapidIO interface
- Supports all RapidIO packet sizes
- Hardware-based physical layer error detection and recovery
- RapidIO 1.3 Specification Error Management Extensions
- Supports Multicast-event control symbol generation and detection
- Designed and verified for 130nm (or better) industry standard process technology
- Interfaces with off-the-shelf SerDes
- Intuitive user interface
More Information
The Serial RapidIO Endpoint IP is available through SLE's sales network. To learn more about the benefits and features of this offering, please email sales@siliconlogic.com or call SLE at 1-908-580-1870.
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