SLE's StackBlaster™ is a placement optimization tool that gives users the ability to very finely control cell placement on large, complex ASIC designs. This tool is for use early in the design cycle and helps ensure predictable, repeatable results throughout the physical design flow. It is especially well suited to handle large, high-speed designs with unique cell placement requirements.
Using widely accepted input and output data formats, StackBlaster supplements the functionality of industry standard automatic placement tools while relying on them for underlying low-level functions. In this way, StackBlaster serves as a complement to existing third party tools, not a replacement.
Highlighted Features
- Standard tool input/output format (LEF, PDEF), technology independent
- Useful when a designer needs to impose placement constraints, which are not easily realized using standard tools
- Allows for the finest of detail such as individual cell placement; necessary in very complex designs
- Can be used to generate placements with a high degree of uniformity among wire lengths of cells
- Provides a means of generating a very tightly controlled layout
- Correlates well with final placement results
Contact Lonnie Heidtke for more information.
